# justCTF2019
Some writeups of justCTF2019
## FSMir (Reverse 157pt)
### Description
We managed to intercept description of some kind of a security module, but our intern does not know this language. Hopefully you know how to approach this problem.
```
E:\vmshare\ctf\justctf2019\reverse\FSMir>python solver.py
Start:
}
?}
t?}
ht?}
ght?}
ight?}
right?}
_right?}
n_right?}
on_right?}
ion_right?}
tion_right?}
ation_right?}
tation_right?}
otation_right?}
notation_right?}
_notation_right?}
y_notation_right?}
cy_notation_right?}
ncy_notation_right?}
ancy_notation_right?}
fancy_notation_right?}
_fancy_notation_right?}
h_fancy_notation_right?}
th_fancy_notation_right?}
ith_fancy_notation_right?}
with_fancy_notation_right?}
_with_fancy_notation_right?}
C_with_fancy_notation_right?}
_C_with_fancy_notation_right?}
t_C_with_fancy_notation_right?}
st_C_with_fancy_notation_right?}
ust_C_with_fancy_notation_right?}
just_C_with_fancy_notation_right?}
_just_C_with_fancy_notation_right?}
s_just_C_with_fancy_notation_right?}
is_just_C_with_fancy_notation_right?}
_is_just_C_with_fancy_notation_right?}
g_is_just_C_with_fancy_notation_right?}
og_is_just_C_with_fancy_notation_right?}
log_is_just_C_with_fancy_notation_right?}
ilog_is_just_C_with_fancy_notation_right?}
rilog_is_just_C_with_fancy_notation_right?}
erilog_is_just_C_with_fancy_notation_right?}
Verilog_is_just_C_with_fancy_notation_right?}
mVerilog_is_just_C_with_fancy_notation_right?}
emVerilog_is_just_C_with_fancy_notation_right?}
temVerilog_is_just_C_with_fancy_notation_right?}
stemVerilog_is_just_C_with_fancy_notation_right?}
ystemVerilog_is_just_C_with_fancy_notation_right?}
SystemVerilog_is_just_C_with_fancy_notation_right?}
{SystemVerilog_is_just_C_with_fancy_notation_right?}
F{SystemVerilog_is_just_C_with_fancy_notation_right?}
TF{SystemVerilog_is_just_C_with_fancy_notation_right?}
CTF{SystemVerilog_is_just_C_with_fancy_notation_right?}
tCTF{SystemVerilog_is_just_C_with_fancy_notation_right?}
stCTF{SystemVerilog_is_just_C_with_fancy_notation_right?}
ustCTF{SystemVerilog_is_just_C_with_fancy_notation_right?}
justCTF{SystemVerilog_is_just_C_with_fancy_notation_right?}
```
## FSMir2 (Reverse 201pt)
### Description
We intercepted yet another security module, this time our intern fainted from just looking at the source code, but it's a piece of cake for a hacker like yourself, right?
```
E:\vmshare\ctf\justctf2019\reverse\FSMir2>python solver2.py
justCTF{I_h0p3_y0u_us3d_v3r1L4t0r_0r_sth...}
```